Gallium nitride (GaN) semiconductor devices are increasingly desirable for power semiconductor devices because of their ability to carry large current and support high voltages. Development of these devices has generally been aimed at high power/high frequency applications. Devices fabricated for these types of applications are based on general device structures that exhibit high electron mobility and are referred to variously as heterojunction field effect transistors (HFET), high electron mobility transistors (HEMT), or modulation doped field effect transistors (MODFET).
A GaN HEMT device includes a nitride semiconductor with at least two nitride layers. Different materials formed on the semiconductor or on a buffer layer cause the layers to have different band gaps. The different material in the adjacent nitride layers also causes polarization, which contributes to a conductive two-dimensional electron gas (2 DEG) region near the junction of the two layers, specifically in the layer with the narrower band gap.
The nitride layers that cause polarization typically include a barrier layer of AlGaN adjacent to a layer of GaN to include the 2 DEG, which allows charge to flow through the device. This barrier layer may be doped or undoped. Because the 2 DEG region exists under the gate at zero gate bias, most nitride devices are normally on, or depletion mode devices. If the 2 DEG region is depleted, i.e. removed, below the gate at zero applied gate bias, the device can be an enhancement-mode device. Enhancement-mode devices are normally off and are desirable because of the added safety they provide and because they are easier to control with simple, low cost drive circuits. An enhancement-mode device requires a positive bias applied at the gate in order to conduct current.
FIG. 1 illustrates a cross-sectional view of a conventional field-effect transistor (FET) 100, and is more fully described in U.S. Patent Application Publication No. 2006/0273347. FET 100 of FIG. 1 includes a substrate 101, an AlN buffer layer 102 formed on the substrate 101, a GaN layer 103 formed on the AN buffer layer 102, an AlGaN barrier layer 104 formed on the GaN layer 103. The gate is formed of a p-type GaN layer 105 formed over part of the AlGaN layer 104, and a heavily doped p-type GaN layer 106 formed on the p-type GaN layer 105. A shortcoming of this device/FET 100 is that the barrier layer (AlGaN layer 104) is partially etched away when the gate (e.g., p-type GaN layer 105) is etched. It is desired to not damage the barrier layer 104, so as to have a uniform barrier layer across the device.
FIG. 2 illustrates a cross-sectional view of a conventional step in formation of a typical enhancement-mode GaN HEMT device 200a, and is more fully described in U.S. Pat. No. 8,404,508. Device 200a of FIG. 2 includes a silicon substrate 11, transition layers 12, GaN buffer material 13, AlGaN barrier material/layer 14, p-type GaN gate layer 15, and gate metal 17. A single photo mask is used to pattern and etch the gate metal 17 and the p-type GaN gate layer 15, resulting in the structure/device 200a shown in FIG. 2. The gate metal 17 and the p-type GaN gate layer 15 are etched by any known technique, e.g., plasma etching, followed by a photoresist strip. The p-type GaN gate layer 15 can be under-etched, leaving about 0 to about 10 nm of the gate material outside of the gate region. The gate layer 15 can also be over-etched, removing about 0 to about 3 nm of the barrier layer 14 outside of the gate region. In the over-etching case, the barrier layer 14 is about 0 to about 3 nm thinner outside of the gate region than that in the gate region. Device 200a has a number of shortcomings: (i) the gate layer 15 thickness has non uniformity from EPI growth; (ii) the wafer fabrication etch rate to gate layer 15 has, non uniformity across a wafer, from wafer to wafer, and from lot to lot; (iii) the non-uniformity in gate layer 15 thickness and etch rate non uniformity lead to either leaving an uneven amount of residual layer 15 material over barrier layer 14 or over-etching and damage of barrier layer 14 elsewhere on the wafer. Again, it is desired to have a uniform barrier layer 14.
FIG. 3 illustrates a cross-sectional view of a conventional step in formation of a typical enhancement-mode GaN transistor device 800, and is more fully described in U.S. Pat. No. 8,946,771. Device 800 of FIG. 3 includes a GaN layer 202, an AlGaN electron supply layer 204 located on top of the GaN layer 202, an AlN etch stop layer 206 located on top of the AlGaN electron supply layer 204, a p-type GaN layer 208 located on top of the AlN etch stop layer 206, and a titanium gate metal 210 located on top of the p-type GaN layer 208. A patterned photoresist (P/R) layer 802 is formed on top of the gate metal 210 to mask a region of the substrate that defines a gate structure of the GaN device, by covering the gate metal 210 in the gate region. As mentioned above, a thin AlN layer 206 is disposed between pGaN layer 208 and AlGaN layer 204 (front barrier). The AlN layer 206 serves as gate pGaN etch stop. This enables over-etching of pGaN to completely etch away pGaN outside of the gate region. Device 800 has the following shortcomings: (a) the AlN layer 206 under the pGaN layer 208 decreases the threshold voltage Vth, and tends to make the device toward depletion-mode (D-mode); and (b) the front barrier (AlGaN layer 204) is not protected by a GaN cap layer. It is desired to have a gate etch stop layer without decreasing Vth. It is also desired to have a GaN cap layer over the front barrier outside of the gate region.
FIG. 4 illustrates a cross-sectional view of a conventional depletion mode HEMT FET 400 as described in S. Heikman et al., “Polarization effects in AlGaN/GaN and GaN/AlGaN/GaN heterostructures,” Journal of Applied Physics, Vol. 93, No. 12, 2003, pp. 10114-10118. Device 400 of FIG. 4 includes a front barrier AlGaN 402 overlying a GaN base 401. A thin GaN cap layer 403 overlies the front barrier AlGaN 402, but only in the gate region. This configuration improves depletion mode HEMT FET performance. However, device/FET 400 is only operable for depletion mode HEMT FETs. It is desired to have an enhancement-mode transistor device with a GaN cap layer outside of the gate region.
It therefore would be desirable to provide an enhancement-mode transistor structure that minimizes or eliminates damage to the underlying barrier layer during gate etching steps, and improves GaN spacer thickness uniformity.